1. Field of the Invention
The present invention relates to a flip-flop circuit, a shift register, an N-bit register, and a logic circuit that are used in a semiconductor integrated circuit.
2. Description of the Prior Art
Among various types of flip-flop circuits, pulse drived flip-flop circuits (PD-FFs) are advantageous in reducing power consumption and simplifying circuit structure.
FIG. 1 shows a PD-FF according to a prior art. An input node N101 receives input data In and is connected to a transfer gate 103, which is connected to an intermediate node N102. The transfer gate 103 is turned on and off in response to an external pulse signal PS and an inverted pulse signal PS each having a given pulse width. Between the intermediate node N102 and an output node N104, a latch circuit 107 is arranged. The latch circuit 107 consists of an output inverter 105 and a feedback inverter 106 that are connected to each other in an antiparallel manner. An output terminal of the latch circuit 107 is equal to the output node N104, which provides output data Out.
When the pulse signal PS indicates 1, the PD-FF transfers the input data In to the intermediate node N102, and when the pulse signal PS indicates 0, holds the input data. By properly adjusting the pulse width of the pulse signal PS, it is possible to reduce power consumption.
FIG. 2 is a circuit diagram showing a logic circuit employing PD-FFs each being the same as the PD-FF of FIG. 1. The PD-FFs 201-1-1 to 201-N-1 are connected in parallel to form an N-bit register, and M stages of such N-bit registers (201-1-1 to 201-N-1, to 201-1-M to 201-N-M) are connected in series to form the logic circuit. A pulse generator (PG) 202 generates a pulse signal PS having a required pulse width according to a clock signal CLK and supplies simultaneously the pulse signal PS directly to all PD-FFs of the first N-bit register and further, through pulse drivers 203-1 to 203-(M-1) to the PD-FFs of the second to Mth N-bit registers.
FIG. 3A is a circuit diagram showing a part A of FIG. 2. The part A includes the PD-FFs 201-1-1 and 201-1-2 connected in series. The PD-FF 201-1-1 consists of a transfer gate 103-1 and a latch circuit 107-1, and the PD-FF 201-1-2 consists of a transfer gate 103-2 and a latch circuit 107-2. The PD-FF 201-1-1 receives a pulse signal PS1 and an inverted pulse signal PS1 and provides output data Out1. The PD-FF 201-1-2 receives a pulse signal PS2 and an inverted pulse signal PS2 and provides output data Out2.
The operation of the part A will be explained with reference to timing charts of FIGS. 3B and 3C. In FIGS. 3B and 3C, T1 is a pulse width of each of the pulse signals PS1 and PS2, T2 is a delay time between the pulse signals PS1 and PS2, and T3 is an output definition period starting when the pulse signal PS1 (PS2) is applied to the gate terminal of the transfer gate 103-1 (103-2) and ending when the output data Out1 (Out2) is provided. T4 is a delay time required for the potential at intermediate node N102-1 (N102-2) to reach a threshold potential of an output inverter in the latch circuit 107-1 (107-2) after an input data In (an output data Out1) arrived at an input node N101 (an output node N104-1) while the transfer gate 103-1 (1032) is in a conduction state.
When the pulse signal PS1 rises to "1", the input data In at the input node N101 is fetched by the PD-FF 201-1-1. After the period T3, the data In arrives at the output node N104-"1", which provides output data Out1 as shown in FIG. 3B. After a predetermined period, if the transfer gate 103-2 of the PD-FF 201-1-2 is turned on, the output data Out1 is fetched by PD-FF 201-1-2, and arrives at an output node N104-2 after the period T3+T4 and is provided as output data Out2. The sum of the pulse width T1 and delay time T2 is a period starting when the transfer gate 103-1 is turned on and ending when the transfer gate 103-2 is turned off. This logic circuit of the prior art is effective to reduce the number of elements of each flip-flop circuit, lighten load on clock nodes, and lower power consumption. The logic circuit, however, has the following problems:
(a) The logic circuit may operate properly if T1+T2&lt;T3+T4. If not so, data will pass from the input node N101 to the output node N104-2. More precisely, if T1+T2&lt;T3+T4 as shown in n FIG. 3B, data A+1 is fetched by PD-FF 201-1-1 when the pulse signal PS1 rises to "1" and the data A+1 is provided as Out1 after the period T3. The pulse signal PS2 falls to "0" before the output data Out1, or A+1 is transferred to the intermediate node N102-2. Hence, "a data-pass-through problem" is not caused. And data A fetched previously by PD-FF 201-1-2 is provided as the output data Out2 after the period T3.
However, if T1+T2&gt;T3+T4 as shown in FIG. 3C, the data A+1 fetched by PD-FF 201-1-1 with the pulse signal PS1 of "1" arrives as data A+1 to the intermediate node N102-2 before the pulse signal PS2 falls to "0". And the data A+1 is further fetched by PD-FF 201-1-2 and provided as the output data Out2, to cause the data-pass-through problem.
(b) The PD-FFs connected in parallel input-output configuration as shown in FIG. 2 increase gate load to make pulse signals loose sharpness. This may cause a data fetch error.
(c) To keep the pulse width T1 narrow, it is necessary to employ pulse drivers that operate at high speed. In FIG. 2, each of the pulse drivers 203-1 to 203-M must drive a pulse signal for all N bits. In this case, the driving capability of each pulse driver must be increased in proportion to the number (N) of bits.